此領域的工作機會請點我

(From 104人力銀行，以Nvidia研發替代役為例，有1/3的工作職缺與測試領域相關)

VLSI Test Technology Workshop 2018

Contact: [TOP OF THE PAGE]

Office		EC9001, Department of Computer Science and Engineering National Sun Yat-sen University, 804, Kaohsiung
Phone	Office	+886-75252000 ext.4320
Phone	Lab	+886-79765846
Cell Phone		+886-972590908
Fax		+886-75254301
Princeton website		Katherine Shu-Min Li, Visiting Research Collaborator in Department of Electrical and Computer Engineering, Princeton University
實驗室方向簡介		Past, Present and Future of Test About EDA&T Lab
		a0950095@g-mail.nsysu.edu.tw smli@mail.cse.nsysu.edu.tw smli@cse.nsysu.edu.tw

Announcement: [TOP OF THE PAGE]

2024	恭賀!! 李淑敏教授指導博士生吳芳其榮獲【2024 IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems】論文接受
2023	恭賀!! 李淑敏教授指導博士生Nadun Sinhabahu榮獲【2023 IEEE International Test Conference】論文接受
2022	恭賀!! 李淑敏教授指導碩士生陳立揚榮獲【2022 IEEE International Test Conference】論文接受
	恭賀!! 李淑敏教授指導碩士生鄭周祥榮獲【2022 IEEE International Test Conference】論文接受
	恭賀!! 李淑敏教授指導博士生Nadun Sinhabahu榮獲【2022 IEEE International Test Conference】論文接受
	恭賀!! 李淑敏教授指導參賽廖翊宇，陳立揚與鄭周祥榮獲NXP AI Innovation Award with Gold Champion
	恭賀!! 李淑敏教授指導碩士生陳立揚，鄭周祥與廖翊宇榮獲【2022 IEEE Transactions on Semiconductor Manufacturing】論文接受
	恭賀!! 李淑敏教授指導碩士生江勖豪與陳立揚榮獲【2022 IEEE Transactions on Semiconductor Manufacturing】論文接受
	恭賀!! 李淑敏教授指導碩士生陳立揚，廖翊宇與鄭周祥榮獲【2022 IEEE Transactions on Semiconductor Manufacturing】論文接受
2021	恭賀!! 李淑敏教授指導碩士生陳立揚與江勖豪榮獲【2021 IEEE International Test Conference】論文接受
	恭賀!! 李淑敏教授指導碩士生廖翊宇，陳立揚與鄭周祥榮獲【2021 IEEE International Test Conference】論文接受
	恭賀!! 李淑敏教授指導碩士生鄭周祥，陳立揚與廖翊宇榮獲【2021 IEEE Transactions on Semiconductor Manufacturing】論文接受
	恭賀!! 李淑敏教授指導碩士生陳立揚，廖翊宇與鄭周祥榮獲【2021 IEEE Transactions on Semiconductor Manufacturing】論文接受
	恭賀!! 李淑敏教授指導碩士生陳立揚，廖翊宇與鄭周祥榮獲【2021 IEEE European Test Symposium】論文接受
2020	恭賀!! 李淑敏教授指導廖翊宇與鄭周祥榮獲【2020 IEEE Semiconductor Manufacturing】IEEE 半導體製造期刊論文接受
	恭賀!! 李淑敏教授指導吳芳其與李建德榮獲【2021 IEEE Design, Automation and Test in Europe Conference】論文接受
	恭賀!! 李淑敏教授指導陳立揚與鄭周祥榮獲【2020 IEEE International Test Conference】論文接受
	恭賀!! 李淑敏教授指導鄭周祥、江勖豪與廖翊宇榮獲【2020 IEEE Trasanction on Semiconductor Manufacturing】IEEE 半導體製造期刊論文接受
	恭賀!! 李淑敏教授指導廖翊宇與鄭周祥榮獲【2020 IEEE European Test Symposium】論文接受
	恭賀!! 李淑敏教授指導專題學生鄭周祥榮獲【2020 IEEE VLSI Test Symposium】論文接受
	恭賀!! 李淑敏教授指導專題學生鄭周祥與陳立揚榮獲【2020 IEEE Design, Automation and Test in Europe Conference】論文接受
2019	恭賀!! 李淑敏教授指導專題學生鄭周祥與碩士生江勖豪榮獲【2019 IEEE International Test Conference】論文接受
2019	恭賀!! 李淑敏教授指導專題學生鄭周祥榮獲【2019 IEEE SWTest Asia】論文接受
2018	恭賀!! 李淑敏教授指導博士班學生李建德榮獲【2018 IEEE Asian Test Symposium】論文接受
	恭賀!! 李淑敏教授指導學生江勖豪榮獲【2018 IEEE International Test Conference in Asia】論文接受
	恭賀!!李淑敏教授指導學生吳佳霖榮獲【2018 IEEE International Symposium on VLSI Design, Automation and Test】論文接受
2017	恭賀!! 李淑敏教授指導學生陳信志、侯博鈞，鄧人豪教授指導學生劉濱翰、劉芸瑄、黃唯豪、陳仕賢，榮獲2017跨領域工程專題競賽與成果展 - 課程組【佳作】
2016	國立台灣大學電機工程系張耀文老師研究生學習秘笈之快快樂樂做研究請點我
	恭賀!!博士班學生李建德榮獲【2016年雲端計算與大數據研討會最佳論文獎】
	恭賀!!李淑敏教授榮獲【2016 IEEE Education Society Mac E. VanValkenburg Award】
	國際合作上海復旦大學教授吳永輝教授來台研究蒞臨本實驗室沈浸台灣八景之一，著作成果斐然請點我
	指導學生：李建德、侯博鈞、楊家豪、陳信志，參加經濟部技術處主辦「2015大專院校專利分析與布局競賽」獲得【潛力獎】
2015	恭賀!!碩一學生李建德榮獲【2016 IEEE VLSI Test Symposium】論文接受
	恭賀!!碩一學生李建德榮獲【2016 IEEE Asia and South Pacific Design Automation Conference 】論文接受
	恭賀!! 李淑敏老師榮升中山大學教授
2014	指導學生：蔡耀宇、林曉慶、李沿槱，參加經濟部技術處主辦「2014大專院校專利分析與布局競賽」獲得【入圍獎】
2014	恭賀!!李淑敏副教授榮升IEEE資深會員【IEEE Senior Member】
2013	恭賀!!李淑敏副教授於【2013大專院校專利分析與布局競賽擔任【EDA＆T】隊伍之指導老師榮獲【潛力獎】
	恭賀!! 李淑敏副教授於【教育部顧問室資訊軟體人才培育先導計畫】擔任【2013年第23次ITSA線上程式設計大賽】指導老師榮獲【績優】團隊
	恭賀!! 李淑敏副教授於【教育部顧問室資訊軟體人才培育先導計畫】擔任【 2013 年第 24 次 ITSA 線上程式設計大賽】指導老師榮獲【績優】團隊
	恭賀!! 李淑敏副教授於【教育部顧問室資訊軟體人才培育先導計畫】擔任【 2013 年第 25 次 ITSA 線上程式設計大賽】指導老師榮獲【績優】團隊
	恭賀!! 李淑敏副教授申請的大專生國科會計畫通過
	恭賀!! 李淑敏副教授指導學生程柏銓同學、郭可驥副教授指導學生許訓嘉同學、與電機系辜德典同學和陳致霖同學參加100 學年度大校院智慧電子系統(IE)設計競賽 - 核心技術組【優等】
2012	恭賀!! 李淑敏老師榮升中山大學副教授
2011	恭賀!! 李淑敏教授指導大學部學生：蔣孟剛、劉家倫、李育賢，參加教育部主辦「99學年度大學校院積體電路電腦輔助設計(CAD)軟體製作競賽」榮獲定題A組-測試與合成組【佳作】

Education: [TOP OF THE PAGE]

(1) B.S., Dept. of Computer Science, Rutgers, the State University of New Jersey
(新澤西州立羅格斯大學布溪校區資訊科學系).

(2) M.S., Dept. of Computer and Information System, National Chiao Tung University
(交通大學資訊科學研究所).

(3) Ph.D., Dept. of Electronics Engineering, National Chiao Tung University
(交通大學電子工程研究所).

Course: [TOP OF THE PAGE]

● Introduction to EDA&T (Selective Course)

● Advanced VLSI & SoC Testing (Selective Course, English )

● Computer Architecture (Required Course in Graduate School)

● Computer Organization (Required and Selective Course, English)

● SoC Design Flow & Tools (Required Course in Graduate School)

● Design for Manufacturability (Selective Course)

● 高科技專利 (Selective Course)

● Engineering Mathematics for Computer Science (Required Course, English)

● SoC Testing (Graduate Course)

● Calculus II (Required Course)

● IC Lab (Required Course in Graduate School)

● Programing Language (Required Course)

● Kernel-Based Machine learning

● QT and Windows Programming

● Big Data Analysis and Practice

● Blockchain Technology (incl. Solidity Labs)

● Computer Architecture (Required Course in Graduate, English)

● Data Structure (Required Course in Undergraduate, English)

Areas of Interest: [TOP OF THE PAGE]

● Testing and Design for Testability: Test Design, ATPG,BIST and DFT, Core and System Test

● Physical Design/Automatic Placement and Routing (APR) : Floorplanning, Routing

● Signal Intergrity (SI, 訊號整合) and Power Intergrity (PI, 功率整合), Crosstalk-Induced Glitch and Delay (串音所致之突波與延遲)

● Computer Architecture & Organization

● Green Electronics System Design, Smart Electronics System Design, Smart Grid System Design

● Design Verification

● Computer Aided Design (CAD), Electronic Design Automation (EDA), Test Automation

● Modeling and Simulation for Interconnect, System in Package (SiP), and 3D IC: Interconnect modeling, Design for Manufacturability, Yield Optimization, Reliability Analysis, Emerging Technologies

● Power/Energy-Aware Embedded Systems Design

● Algorithm Design & implementation (演算法分析設計與實作)

● Network-On-Chip Program Design (網路晶片程式設計)

● Graph Theory Program Design (圖論程式設計)

● GUI Program Design (圖形介面程式設計)

● Electronic Program Design (電子設計自動化)

● IC Design & Testing (積體電路設計與測試)

● Automatic Placement and Routing (APR, 平面規劃與繞線器設計)

● 3D IC & System-In-Package Design (三維晶片與系統層級封裝設計)

● Cloud Computing (雲端計算), Security of Cloud Computing (雲端計算安全)

● Financial Engineering (財務工程) , High-frequency trading (高頻交易), Automatic Trading (交易自動化), Algorithmic trading (程式交易), Financial 4.0 (金融 4.0)

● Kernel-Based Machine learning (核心基礎的機器學習)

● GUI (Graphical User Interface) and Windows Programming (圖形用戶介面和視窗程式訓練)

● CIM (Computer-Integrated Manufacturing System), Industries 4.0 (工業 4.0)

● MCS/MES (Material Control/Execution System) modeling & optimization; smart manufacturing (智慧製造), Manufacturing Automation (生產自動化))

● Block Chain Technology and Application (區塊鏈基礎研究與應用)

● Intelligent Vehicle (智慧車用電子), Security of Intelligent Vehicle (智慧車用電子安全)

● Time Series Predictor and AI Study (時間序列預測器與人工智慧相關研究)

● Hardware Trojan and Physical Unclonable Function (硬體木馬與物理不可複製函數, 硬體安全設計與測試)

● AI Hardware Acceleration, AI Hardware Parallel Computing

● Automatic Package Router (自動封裝繞線器), Automatic Substrate Router (自動基底層繞線器)

● AI Router (人工智慧實體繞線器)

● Hardware Security (硬體安全)

● AI-Driven Wafer Test (人工智慧導向晶圓測試)

● FinTech Blockchain and Automation (金融區塊鏈與自動交易系統)

● Field Programmable Gate Array (現場可程式化邏輯閘陣列)

● System On Programmable Chip (可程式化單晶片系統)

● AI Accelerator Design (人工智慧加速器設計)

● High Frequency Trading Related Research (高頻交易相關研究)

Related Publications:: [TOP OF THE PAGE]

International Journals International Conferences Domestic Conferences

I. International Journals:
[1] K. S.-M. Li, C. Su, Y.-W. Chang, C.-L. Lee, and J.-E Chen, “IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 25, No. 11, pp. 2513-2525, Nov. 2006. doi : 10.1109/TCAD.2006.881330
[2] K. S.-M. Li, C.-L. Lee, C. Su, and J.-E Chen, “IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection,” Journal of Electronic Testing: Theory and Applications (JETTA), Vol. 23, Issue 4, pp. 341-355, Aug. 2007. doi : 10.1007/s10836-007-0759-5
[3] K. S.-M. Li, Y.-M. Chang, C.-L. Lee, C. Su, and J.-E Chen, “Multilevel Full-Chip Routing with Testability and Yield Enhancement,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 26, Issue. 9, pp. 1625-1636, Sep. 2007. doi : 10.1109/TCAD.2007.895587
[4] S.-J. Wang, P-C. Tsai, H.-M. Weng and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” International Journal of Electrical Engineering (IJEE), Vol. 15, No. 2, pp.71-78, Apr. 2008. doi : 10.1109/ATS.2007.33
[5] S.-J. Wang, K.-L. Peng, K.-C. Hsiao and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Launch-off-Shift Transition Test Coverage,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 13, Issue. 4, Article 64, pp.64:1-64:16, Sep. 2008. doi : 10.1145/1391962.1391972
[6] K. S.-M. Li, C.-L. Lee, C. Su, and J. E. Chen, “A Unified Detection Scheme for Crosstalk Effects in Interconnection Bus,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 17, Issue. 2, pp.306-311, Feb. 2009. doi : 10.1109/TVLSI.2008.2004548
[7] S.-J. Wang, K. S.-M. Li, S.-C. Chen, H.-Y. Shiu and Y.-L. Chu, “Scan-Chain Partition for High Test-Data Compressibility and Low Shift Power Under Routing Constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 28, Issue 5, pp. 716-727, May 2009. doi : 10.1109/TCAD.2009.2015741
[8] K. S.-M. Li, “Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction Under Output Constraint,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 29, Issue. 4, pp. 618-626, Apr. 2010. doi : 10.1109/TCAD.2010.2042896
[9] K. S.-M. Li and J.-Y. Huang, “Synthesizing Multiple Scan Trees to Optimize Test Application Time,” IEEE Design & Test of Computers (D&T), Vol. 28, Issue 2, pp. 62-69, Mar./Apr. 2011. doi : 10.1109/MDT.2011.38
[10] K. S.-M. Li, C.-Y. Pai, and L.-B. Chen, “Maximal Interconnect Resilient Methodology for Fault Tolerance, Yield, and Reliability Improvement in Network on Chip,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (IEICE Trans. Fundamentals), Vol.E94-A, No.12, pp. 2649-2658, Dec. 2011. doi : 10.1587/transfun.E94.A.2649
[11] K. S.-M. Li and Y.-Y. Liao, “Layout-Aware Multiple Scan Tree Synthesis for 3-D SoCs,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 31, No. 12, pp. 1930-1934, Dec. 2012. doi : 10.1109/TCAD.2012.2208644
[12] K. S.-M. Li, “CusNoC: Fast Full-Chip Custom NoC Generation,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No. 4, pp. 692-705, Apr. 2013. doi : 10.1109/TVLSI.2012.2195688
[13] K. S.-M. Li and Y.-Y. Liao, “IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, No. 7, pp.1333-1337, July 2013. doi : 10.1109/TVLSI.2012.2210451
[14] K. S.-M. Li, “Oscillation and Transition Tests for Synchronous Sequential Circuits,” IEEE Transactions on Very Large Scale Integration Systems (TVLSI), Vol. 21, Issue 12, pp. 2338-2343, Dec. 2013. doi : 10.1109/TVLSI.2012.2230654
[15] K. S.-M. Li, Y.-C. Ho and L.-B. Chen, “Interconnect-Driven Floorplanning with Noise-Aware Buffer Planning,” IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences (IEICE Trans. Fundamentals), Vol. E96-A, No. 12, pp. 2467-2474, Dec. 2013. doi : 10.1587/transfun.E96.A.2467
[16] K.-T. Yang, W.-K. Lai, K. S.-M. Li and Y.-C. Lin, “Event-Based Clustering Architecture for Power Efficiency in Wireless Sensor Networks,” International Journal of Distributed Sensor Networks (IJDSN), Vol. 2014, pp. 1-12, May 2014. doi : 10.1155/2014/612590
[17] K. S.-M. Li, Y.-C. Ho, Y.-W. Yang and L.-B. Chen, “An Oscillation-Based On-Chip Temperature-Aware Dynamic Voltage and Frequency Scaling Scheme in System-on-a-Chip,” IEICE Transactions on Information and Systems (IEICE Trans. Inf.＆Syst.), Vol. E97-D, No. 9, pp. 2320-2329, Sep. 2014. doi : 10.1587/transinf.2013LOP0016
[18]L.-B. Chen, H.-Y. Li, W.-J. Chang, J.-J. Tang, and K. S.-M. Li, “WristEye: Wrist-Wearable Devices and a System for Supporting Elderly Computer Learners,” IEEE Access, Vol. 4, pp. 1454-1463, Apr. 2016. doi : 10.1109/ACCESS.2016.2553838
[19]L.-B. Chen, W.-J. Chang, K.-M. Lee, C.-W. Huang, and K. S.-M. Li, “A Comprehensive Medicine Management System with Multiple Sources in a Nursing Home in Taiwan,” IEICE Transactions on Information and Systems (IEICE Trans. Inf.＆Syst.), Vol. E99.D, Issue 6, pp. 1447-1454, June 2016. doi : 10.1587/transinf.2015CBP0006
[20] K. S.-M. Li and S.-J. Wang, “Design Methodology of Fault-Tolerant Custom 3D Network-on-Chip,” ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol. 22, Issue 4, Article No.63, pp. 63.1-63.20, July 2017. doi : 10.1145/3054745
[21] K. S.-M. Li, S.-J. Wang, R.-T. Gu and B.-C. Cheng, “Layout-Aware Optimized Prebond Silicon Interposer Test Synthesis,” IEEE Design & Test (D&T), Vol. 34, Issue 6, pp. 77-83, Dec. 2017. doi : 10.1109/MDAT.2015.2471296
[22] J.-D. Li, C.-H. Kuo, G.-R. Lu, S.-J. Wang, K. S.-M. Li, T.-Y. Ho, H.-M. Chen and S.-Y. Hu, "Co-Placement Optimization in Sensor-Reusable Cyber-Physical Digital Microfluidic Biochips." Microelectronics Journal,Vol. 83, pp. 185-196, Jan. 2019. doi : 10.1016/j.mejo.2018.08.005
[23] S.-J. Wang, K.-T. Yeh, and K. S.-M. Li, “Exploiting Distribution of Unknown Values in Test Responses to Optimize Test Output Compactors,” Integration, the VLSI Journal, Vol. 65, pp. 389-394, Mar. 2019. doi : 10.1016/j.vlsi.2017.12.008
[24] K. S.-M. Li, N. C.-Y. Tsai, K. C.-C. Cheng, X.-H. Jiang, P. Y.-Y. Liao, S.-J. Wang, A. Y.-A Huang, L. Chou and C.-S. Lee, "TestDNA: Novel Wafer Defect Signature for Diagnosis and Pattern Recognition," IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 33, Issue 3, pp. 383-390, Aug. 2020. doi : 10.1109/TSM.2020.2992927
[25] T.-P. Hong, C.-Y. Lin, W.-M. Huang, K. S.-M. Li, S.-L. Wang, and J. C.-W. Lin, “Using Tree Structure to Mine High Temporal Fuzzy Utility Itemsets,” IEEE Access, Vol. 8, pp. 153692-153706, Aug. 2020. doi : 10.1109/ACCESS.2020.3018155
[26] K. S.-M. Li, P. Y.-Y. Liao, K. C.-C. Cheng, L. L.-Y. Chen, S.-J. Wang, A. Y.-A. Huang, L. Chou, G. C.-H. Han, J. E Chen, H.-C. Liang, and C.-L. Hsu, "Hidden Wafer Scratch Defects Projection for Diagnosis and Quality Enhancement," IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 34, issue 1, pp. 9-16, Feb. 2021. doi : 10.1109/TSM.2020.3040998
[27] K. C.-C. Cheng, L. L.-Y. Chen, J.-W. Li, K. S.-M. Li, N. C.-Y. Tsai, S.-J. Wang, A. Y.-A. Huang, L. Chou, C.-S. Lee, J. E Chen, H.-C. Liang, and C.-L. Hsu, "Machine Learning Based Detection Method for Wafer Test Induced Defects," IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 34, issue 2, pp. 161-167, May 2021. doi : 10.1109/TSM.2021.3065405
[28] S.-J. Wang, Y.-S. Chen, and K. S.-M. Li, "Modeling Attack Resistant PUFs Based on Adversarial Attack Against Machine Learning," IEEE Journal on Emerging and Selected Topics in Circuits and Systems (IEEE J. Emerg. Sel. Top. Circuits Syst.), Vol. 11, issue 2, pp. 306-318, June. 2021. doi : 10.1109/JETCAS.2021.3062413
[29] T.-P. Hong, C.-Y. Lin, W.-M. Huang, K. S.-M. Li, S.-L. Wang, and J. C.-W. Lin, "A One-Phase Tree-Structure Method to Mine High Temporal Fuzzy Utility Itemsets," Applied Sciences (Appl. Sci.), Vol. 12, issue 6, 2821, Mar. 2022. doi : 10.3390/app12062821
[30] K. S.-M. Li, L. L.-Y. Chen, P. Y.-Y. Liao, S.-J. Wang, A. Y.-A. Huang, L. Chou, N. C.-Y. Tsai, K. C.-C. Cheng, G. C.-H. Han, C.-S. Lee, J. E Chen, H.-C. Liang, and C.-L. Hsu, "Wafer Scratch Pattern Reconstruction for High Diagnosis Accuracy and Yield Optimization," IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 35, issue 2, pp. 272-281, May 2022. doi : 10.1109/TSM.2022.3146857
[31] K. S.-M. Li, X.-H. Jiang, L. L.-Y. Chen, S.-J. Wang, A. Y.-A. Huang, J. E Chen, H.-C. Liang, and C.-L. Hsu, "Wafer Defect Pattern Labeling and Recognition Using Semi-supervised Learning," IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 35, issue 2, pp. 291-299, May 2022. doi : 10.1109/TSM.2022.3159246
[32] K. S.-M. Li, L. L.-Y. Chen, K. C.-C. Cheng, P. Y.-Y. Liao, S.-J. Wang, A. Y.-A. Huang, L. Chou, N. C.-Y. Tsai, and C.-S. Lee, "TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning," IEEE Transactions on Semiconductor Manufacturing (TSM), Vol. 35, issue 2, pp. 372-374, May 2022. doi : 10.1109/TSM.2022.3145855
[33] Y.-H. Chuang, J.-H. Su, D.-H. Han, Y.-W. Liao, Y.-C. Lee, Y.-F. Cheng, T.-P. Hong, K. S.-M. Li, H.-Y. Ou, Y. Lu, and C.-C. Wang, "Effective Natural Language Processing and Interpretable Machine Learning for Structuring CT Liver-Tumor Reports," IEEE Access, Vol. 10, pp. 116273-116286, Nov. 2022. doi : 10.1109/ACCESS.2022.3218646
[34] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, "Design-for-reliability and on-the-fly fault tolerance procedure for paper-based digital microfluidic biochips with multiple faults," Integration, the VLSI Journal, Vol. 89, pp. 185-196, Mar. 2023. doi : 10.1016/j.vlsi.2022.11.013
[35] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, "Enhanced Watermarking for Paper-Based Digital Microfluidic Biochips," ACM Transactions on Design Automation of Electronic Systems (TODAES),Vol. 29, issue 4, pp. 1 - 27, June 2024. doi : 10.1145/3661309
[36] K. S.-M. Li, F.-C. Wu, J.-D. Li, S.-J. Wang, "Reinforcement Learning Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol. 43, issue 8, pp. 2465 - 2478, Aug. 2024. doi : 10.1109/TCAD.2024.3370652 [BACK TO TOP]

II. International Conferences:
[1] K. S.-M. Li, Y.-H. Cherng, and Y.-W. Chang, “Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 423-426, Jan. 2003. doi : 10.1145/1119772.1119856
[2] B.-S. Liu, C.-L. Lee, K. S.-M. Li, and J.-E Chen, “Crosstalk Fault Testing by Using Oscillation Ring Testing Methodology for SOC Interconnection Lines,” in Proc. IEEE International Test Synthesis Workshop (ITSW), 2004. doi : https://static.aminer.org/pdf/PDF/000/220/364/a_fault_simulation_method_for_crosstalk_faults_in_synchronous_sequential.pdf
[3] K. S.-M. Li, C.-L. Lee, C. Su, and J.-E Chen, “A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-micron VLSI,” in Proc. IEEE Asia Test Symposium (ATS), pp. 145-150, Nov. 2004. doi : 10.1109/ATS.2004.19
[4] K. S.-M. Li, C.-L. Lee, C. Su, and J.-E Chen, “Oscillation Ring Based Interconnect Test Scheme for SOC,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 184-187, Jan. 2005. doi : 10.1109/ASPDAC.2005.1466154
[5] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su, and J.-E Chen, “Multilevel Full-Chip Routing with Testability and Yield Enhancement,” in Proc. ACM/IEEE International Workshop on System Level Interconnect Prediction (SLIP), pp. 29-36, Apr. 2005. doi : 10.1145/1053355.1053362
[6] K. S.-M. Li, C.-L. Lee, C. Su, and J.-E Chen, “Finite State Machine Synthesis for At-Speed Oscillation Testability,” in Proc. IEEE Asia Test Symposium (ATS), pp. 360-365, Dec. 2005. doi : 10.1109/ATS.2005.60
[7] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su, and J.-E Chen, “IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 366-371, Jan. 2006. doi : 10.1109/ASPDAC.2006.1594710
[8] K.-L. Peng, S.-J. Wang, and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage,” in Proc. IEEE Asia Test Symposium (ATS), pp. 169-174, Nov. 2006. doi : 10.1109/ATS.2006.261016
[9] S.-J. Wang, Y.-T. Chen, and K. S.-M. Li, “Low Capture Power Test Generation for Launch-off-Capture Transition Test Based on Don’t-Care Filling,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 3683-3686, May 2007. doi : 10.1109/ISCAS.2007.378642
[10] X.-L. Li, S.-J. Wang, and K. S.-M. Li, “Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,” in Proc. IEEE Asian Test Symposium (ATS), pp. 129-132, Oct. 2007. doi : 10.1109/ATS.2007.37
[11] S.-J. Wang, P.-C. Tsai, H.-M. Weng, and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” in Proc. IEEE Asian Test Symposium (ATS), pp. 95-98, Oct. 2007. doi : 10.1109/ATS.2007.33
[12] S.-J. Wang, S.-C. Chen, and K. S.-M. Li, “Design and Analysis of Skewed-Distribution Scan Chain Partition for Improved Test Data Compression,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2641-2644, May 2008. doi : 10.1109/ISCAS.2008.4541999
[13] K. S.-M. Li and J.-Y. Huang, “Interconnect-Driven Layout-Aware Multiple Scan Tree Synthesis for Test Time, Data Compression and Routing Optimization,” in Proc. IEEE Asian Test Symposium (ATS), pp. 63-68, Nov. 2008. doi : 10.1109/ATS.2008.80
[14] Y.-W. Yang and K. S.-M. Li, “Temperature-Aware Dynamic Frequency and Voltage Scaling for Reliability and Yield Enhancement,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp. 49-54, Jan. 2009. doi : 10.1109/ASPDAC.2009.4796440
[15] S.-J. Wang, S.-J. Huang, and K. S.-M. Li, “Static and Dynamic Test Power Reduction in Scan-Based Testing,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 56-59, Apr. 2009. doi : 10.1109/VDAT.2009.5158094
[16] K. S.-M. Li, M.-H. Hsieh, and S.-J. Wang, “Level Converting Scan Flip-Flops,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2505-2508, May 2009. doi : 10.1109/ISCAS.2009.5118310
[17] K.-L. Fu, S.-J. Wang, and K. S.-M. Li, “Low Peak Power ATPG for n-Detection Test,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1993-1996, May 2009. doi : 10.1109/ISCAS.2009.5118182
[18] K. S.-M. Li, Y.-C. Hung, and J.-Y. Huang, “Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint,” in Proc. IEEE Asian Test Symposium (ATS), pp. 231-236, Nov. 2009. doi : 10.1109/ATS.2009.60
[19] K. S.-M. Li, Y.-Y. Liao, Y.-W. Liu, and J.-Y. Huang, “IEEE 1500 Compatible Interconnect Test with Maximal Test Concurrency,” in Proc. 18th IEEE Asian Test Symposium (ATS), pp. 269-274, Nov. 2009. doi : 10.1109/ATS.2009.67
[20] C.-C. Wang, K. S.-M. Li, and S.-J. Wang, “A 1.8 V to 3.3 V Level-Converting Flip-Flop Design for Multiple Power Supply Systems,” in Proc. IEEE International Symposium on Integrated Circuits (ISIC), pp. 61-64, Dec. 2009. doi : https://ieeexplore.ieee.org/document/5403867
[21] C.-Y. Pai and K. S.-M. Li, “Maximal Resilience for Reliability Enhancement in Interconnect Structure,” in Proc. Workshop on Synthesis and System Integration of Mixed Information Technologies (SASIMI), pp. 296 - 301, Oct. 2010.
[22] C.-Y. Pai and K. S.-M. Li, “Maximal Resilience for Reliability and Yield Enhancement in Interconnect Structure,” in Proc. IEEE Asian Test Symposium (ATS), pp. 261-266, Dec. 2010. doi : 10.1109/ATS.2010.53
[23] K. S.-M. Li, S.-Y. Chen, L.-B. Chen, and R.-T. Gu, “A Fast Custom Network Topology Generation with Floorplanning for NoC-based Systems,” in Proc. IEEE International Conference on Integrated Circuits Design and Technology (ICICDT), pp. 1-4, May 2011. doi : 10.1109/ICICDT.2011.5783208
[24] Y.-X. Zheng, P.-P. Kan, L.-B. Chen, K.-Y. Hsieh, B.-C. Cheng, and K. S.-M. Li , “Fault Tolerant Application-Specific NoC Topology Synthesis for Three-Dimensional Integrated Circuits,” in Proc. IEEE International SoC Conference (SOCC), pp. 296-301, Sep. 2011. doi : 10.1109/SOCC.2011.6085088
[25] K.-Y. Hsieh, B.-C. Cheng, R.-T. Gu, and K. S.-M. Li, “Fault-Tolerant Mesh for 3D Network on Chip,” in Proc. IEEE International Microsystems, Packaging, Assembly and Circuits Technology conference (IMPACT), pp. 214-217, Oct. 2011. doi : 10.1109/IMPACT.2011.6117292
[26] C.-Y. Pai, R.-T. Gu, L.-B. Chen, B.-C. Chen, and K. S.-M. Li, “A Unified Interconnects Testing Scheme for 3D Integrated Circuits,” in Proc. IEEE Asian Test Symposium (ATS), pp. 195-200, Nov. 2011. doi : 10.1109/ATS.2011.38
[27] S.-J. Wang, H.-H. Hsu, and K. S.-M. Li, “Low-Power Delay Test Architecture for Pre-Bond Test,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2321-2324, May 2012. doi : 10.1109/ISCAS.2012.6271759
[28] B.-C. Cheng, K. S.-M. Li, and S. -J. Wang, “De Bruijn Graph-Based Communication Modeling for Fault Tolerance in Smart Grids,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems Proceedings (APCCAS), pp. 623-626, Dec. 2012. doi : 10.1109/APCCAS.2012.6419112
[29] M.-K. Chiang and K. S.-M. Li, “Intelligent Home Management in the Smart Grids,” in Proc. IEEE Asia Pacific Conference on Circuits and Systems Proceedings (APCCAS), pp. 567-570, Dec. 2012. doi : 10.1109/APCCAS.2012.6419098
[30] R.-T. Gu, C.-Y. Ho, K. S.-M. Li, Y.-C. Ho, L.-B. Chen, K.-Y. Hsieh, J.-J Huang, B.-C. Cheng, S.-J. Wang, and Z.-H. Gao, “A Layout-Aware Test Methodology for Silicon Interposer in 3D System-in-a-Package,” in Proc. IEEE International Symposium on Next-Generation Electronics (ISNE), pp. 41-44, Feb. 2013. doi : 10.1109/ISNE.2013.6512281
[31] Y. Ho, K. S.-M. Li, and S.-J. Wang, “A 0.3 V Low-power Temperature-insensitive Ring Oscillator in 90 nm CMOS Process,” in Proc. IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp. 161-164, Apr. 2013. doi : 10.1109/VLDI-DAT.2013.6533838
[32] S.-J. Wang, Y.-S. Chen, and K. S.-M. Li, “Low-Cost Testing of TSVs in 3D Stacks with Pre-bond Testable Dies, ” in Proc. IEEE International Symposium on VLSI Design, Automation & Test (VLSI-DAT), pp. 366-369, Apr. 2013. doi : 10.1109/VLDI-DAT.2013.6533888
[33] S.-J. Wang, C.-H Lin, and K. S.-M. Li, “Synthesis of 3D clock tree with pre-bond testability,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2654-2657, May 2013. doi : 10.1109/ISCAS.2013.6572424
[34] K. S.-M. Li, C.-Y. Ho, S.-J. Wang, R.-T. Gu, J.-J. Huang, B.-C. Cheng, and Y.-C. Ho, “A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package,” in Proc. IEEE Asian Test Symposium (ATS), pp. 159-166, Nov. 2013. doi : 10.1109/ATS.2013.38
[35] Y.-C. Ho, K. S.-M. Li, and S.-J. Wang, “Leakage Monitoring Technique in Near-threshold Systems with a Time-based Bootstrapped Ring Oscillator,” in Proc. IEEE Asian Test Symposium (ATS), pp. 91-96, Nov. 2013. doi : 10.1109/ATS.2013.25
[36] K.-Y. Hsieh, L.-B. Chen, and K. S.-M. Li, “A Timing-Aware Unified Methodology for Small Delay Defects Testing,” in Proc. IEEE International Symposium on Next-Generation Electronics (ISNE), May 2014.
[37] S.-J. Wang, T.-H. Tzeng, and K. S.-M. Li, “Fast and Accurate Statistical Static Timing Analysis,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2555-2558, June 2014. doi : 10.1109/ISCAS.2014.6865694
[38] L.-B. Chen, J.-H. Chang, C.-H. Chuang, C.-H. Chuang, Y.-C. Tseng, C.-L. Hung, C.-W. Wu, and K. S.-M. Li, “Development of a Dual-Mode Visible Light Communications Wireless Digital Conference System,” in Proc. IEEE International Symposium on Consumer Electronics (ISCE), pp. 1-2, June 2014. doi : 10.1109/ISCE.2014.6884377
[39] C.-H. Chuang, T.-H. Lin, L.-B. Chen, T.-L. Lee, C.-H. Chuang, K. S.-M. Li, C.-L. Hung, and C.-W. Wu, “A Hybrid Multi-functions Digital Public Address System with Earthquake Early Warning,” in Proc. International Conference on Intelligent Information Hiding and Multimedia Signal Processing (IIHMSP), pp. 171-174, Aug. 2014. doi : 10.1109/IIH-MSP.2014.49
[40] S.-J. Wang, C.-W. Kao, and K. S.-M. Li, “Improving Output Compaction Efficiency with High Observability Scan Chains,” in Proc. IEEE Asian Test Symposium (ATS), pp. 324-329, Nov. 2014. doi : 10.1109/ATS.2014.66
[41] K. S.-M. Li, S.-J. Wang, J.-L. Wu, C.-Y. Ho, Y. Ho, R.-T. Gu, and B.-C. Cheng, “Optimized Pre-bond Test Methodology for Silicon Interposer Testing,” in Proc. IEEE Asian Test Symposium (ATS), pp.13-18, Nov. 2014. doi : 10.1109/ATS.2014.15
[42] H.-C. Chen, C.-R. Wu, K. S.-M. Li, and K.-J. Lee, “A Breakpoint-Based Silicon Debug Technique with Cycle-Granularity for Handshake-Based SoC,” in Proc. IEEE Design, Automation & Test in Europe (DATE), pp.9-13, Mar. 2015. doi : https://ieeexplore.ieee.org/document/7092589
[43] S.-J. Wang, C.-W. Kao, and K. S.-M. Li, “High Observability Scan Chains with Improving Output Compaction Efficiency,” in Proc. Workshop on Synthesis and System Integration of Mixed Integration of Mixed Information Technologies (SASIMI), pp.171-176, Mar. 2015.
[44] K. S.-M. Li, S.-J. Wang, X.-Y. Li, R.-T. Gu, and B.-C. Cheng, “Pre-bond Interposer Test Methodology for System in Package,” in Proc. Workshop on Synthesis and System Integration of Mixed Integration of Mixed Information Technologies (SASIMI), pp.151-156, Mar. 2015.
[45] L.-B. Chen, H.-Y. Li, W.-J. Chang, J.-J. Tang, and K. S.-M. Li, “An Intelligent Vehicular Telematics Platform for Vehicle Driving Safety Supporting System,” in Proc. International Conference on Connected Vehicles and Expo (ICCVE), pp.210-211, Oct. 2015. doi : 10.1109/ICCVE.2015.9
[46] L.-B. Chen, B.-C. Cheng, Y.-C. Wang, K. S.-M. Li, and J.-J. Tang, “An Efficient Fault Tolerance Path Finding Algorithm for Improving the Robustness of Multichannel Wireless Mesh Networks,” in Proc. IEEE International Conference on Consumer Electronics (ICCE), pp.524-525, Jan. 2016. doi : 10.1109/ICCE.2016.7430714
[47] L.-B. Chen, M.-K. Chiang, C.-L. Liu, K. S.-M. Li, and J.-J. Tang, “An Adaptive Residential Energy Management Scheme in the Smart Home,” in Proc. IEEE International Conference on Consumer Electronics (ICCE), pp.257-258, Jan. 2016. doi : 10.1109/ICCE.2016.7430605
[48] L.-B. Chen, C.-W. Tsai, W.-J. Chang, Y.-M. Cheng, and K. S.-M. Li, “A Real-time Mobile Emergency Assistance System for Helping Deaf-mute People/Elderly Singletons,” in Proc. IEEE International Conference on Consumer Electronics (ICCE), pp.45-46, Jan. 2016. doi : 10.1109/ICCE.2016.7430516
[49] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Congestion-and Timing-Driven Droplet Routing for Pin-Constrained Paper-Based Microfluidic Biochips,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), pp.593-598, Jan. 2016. doi : 10.1109/ASPDAC.2016.7428076
[50] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Test and Diagnosis of Paper-Based Microfluidic Biochips,” in Proc. IEEE VLSI Test Symposium (VTS), pp.1-6, Apr. 2016. doi : 10.1109/VTS.2016.7477273
[51]H.-Y. Li, L.-B. Chen, W.-J. Chang, J.-J. Tang, and K. S.-M. Li, “Design and Development of an Extensible Multi-protocol Automotive Gateway,” in Proc. IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), pp.1-2, May 2016. doi : 10.1109/ICCE-TW.2016.7521011
[52] L.-B. Chen, W.-J. Chang, J.-P. Su, J.-Y. Ciou, Y.-J. Ciou, C.-C. Kuo, and K. S.-M. Li, “A Wearable-glasses-based Drowsiness-fatigue-detection System for Improving Road Safety,” in Proc. IEEE Global Conference on Consumer Electronics (GCCE), pp.257-258, Oct. 2016. doi : 10.1109/GCCE.2016.7800456
[53] S.-J. Wang, T.-J. Choi, and K. S.-M Li, “Side-Channel Attack on Flipped Scan Chains,” in Proc. IEEE Asian Test Symposium (ATS), pp.67-72, Nov. 2016. doi : 10.1109/ATS.2016.43
[54] S.-J. Wang, J.-Y. Wei, S.-H. Huang, and K. S.-M. Li, “Test Generation for Combinational Hardware Trojans,” in Proc. IEEE Asian Hardware Oriented Security and Trust Symposium (AsianHOST), pp.1-6, Dec. 2016. doi : 10.1109/AsianHOST.2016.7835569
[55] K. S.-M. Li, et. al., “Internet of Things Security and Challenges,” in Proc. IEEE China Semiconductor Technology International Conference (CSTIC), pp. 175-178, Mar. 2017.
[56] S.-J. Wang, K.-T. Yeh, and K. S.-M. Li, “Exploiting Distribution of Unknown Values in Test Responses to Optimize Test Output Compactors,” in Proc. IEEE China Semiconductor Technology International Conference (CSTIC), Mar. 2017.
[57] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Design-for-Testability for Paper-based Digital Microfluidic Biochips,” in Proc. IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFT), pp.1-1, Oct. 2017. doi : 10.1109/DFT.2017.8244448
[58] S.-J. Wang, H.-H. Chen, C.-H. Lien, and K. S.-M. Li, “Testing Clock Distribution Networks,” in Proc. IEEE Asian Test Symposium (ATS), pp. 163-168, Nov. 2017. doi : 10.1109/ATS.2017.40
[59] J.-L. Wu, K. S.-M. Li, S.-J. Wang, and T.-Y. Ho, “SOLAR: Simultaneous Optimization of Control-Layer Pins Placement and Channel Routing in Flow-Based Microfluidic Biochips,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), pp. 1-4, Apr. 2018. doi : 10.1109/VLSI-DAT.2018.8373234
[60] S.-J. Wang, C.-H. Lien, and K. S.-M. Li, “Register PUF with No Power-Up Restrictions,” in Proc. IEEE International Symposium on Circuits and Systems (ISCAS), pp. 1-5, May 2018. doi : 10.1109/ISCAS.2018.8351052
[61] K. S.-M. Li, R.-Y. Chen, X.-H. Jiang, S.-J. Wang, S.-W. Lee, C.-L. Hsu, and C.-T. Sun, “DAN: Anomaly Detection in Fully Automatic Smart Manufacturing Systems Using Hybrid DWT-Based Predictive Time-Series Analytics,” in Proc.IEEE International Test Conference in Asia (ITC-Asia), pp.1-5, Aug. 2018.
[62] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.Y- Ho, “Digital Rights Management for Paper-Based Microfluidic Biochips,” in Proc. IEEE Asian Test Symposium (ATS), Oct. 2018. doi : 10.1109/ATS.2018.00042
[63] S.-J. Wang, K.-Y Hsu, C.-Y. Liu, and K. S.-M. Li, "Combinational Hardware Trojan Construction and Layout-Aware Test Generation," in Proc. IEEE Asian Test Symposium (ATS), Oct. 2018.
[64] S.-J. Wang, Y.-S. Chen, and K. S.-M. Li, “Adversarial Attack against Modeling Attack on PUFs,” in Proc. IEEE Design Automation Conference (DAC), pp. 1-6, June 2019. doi : 10.1145/3316781.3317761
[65] K. S.-M. Li, K. C.-C. Cheng, A. Y.-A. Huang, C.-Y. Tsai, S.-J. Wang, P. Y.-Y. Liao, L. Chou, and C.-S. Lee, "Wafer Defect Diagnosis with Test Big Data Driven Techniques", in Proc. Semiconductor Wafer Test Asia (SWTest Asia), Oct. 2019.
[66] A. Y.-A. Huang, K. S.-M. Li, S.-J. Wang, C.-Y. Tsai, K. C.-C. Cheng, X.-H. Jiang, L. Chou, and C.-S. Lee, “TestDNA: Novel Wafer Defect Signature for Diagnosis and Yield Learning,” in Proc. IEEE International Test Conference (ITC), Nov. 2019. doi : 10.1109/ITC44170.2019.9000166
[67] T.-P. Hong, C.-Y. Lin, W.-M. Huang, K. S.-M. Li, S.-L. Wang, and J. C.-W. Lin, “Mining Temporal Fuzzy Utility Itemsets by Tree Structure,” in Proc. IEEE International Conference on Big Data (IEEE BigData), Dec. 2019. doi : 10.1109/BigData47090.2019.9006317
[68] K. C.-C. Cheng, K. S.-M. Li, A. Y.-A. Huang, J.-W. Li, L. L.-Y. Chen, N. C.-Y. Tsai, S.-J. Wang, C.-S. Lee, Leon Chou, P. Y.-Y Liao, H.-C. Liang, and Jwu E Chen, “Wafer-Level Test Path Pattern Recognition and Test Characteristics for Test-Induced Defect Diagnosis,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Mar. 2020. doi : 10.23919/DATE48585.2020.9116546
[69] P.-Y. Huang, C.-S. Hsu, T.-P. Hong, Y.-Z. Wang, S.-F. Huang, and K. S.-M. Li, "Automatic Parameter Setting in Hough Circle Transform," in Proc. IEEE Asian Conference on Intelligent Information and Database Systems (ACIIDS), Mar. 2020. doi : 10.1007/978-3-030-41964-6_45
[70] S. Y.-S. Chen, J. E. Chen, T.-Y. Lu, S.-T. Huang, H.-C. Liang, K. S.-M. Li, and C. Y.-H. Liu, “Analysis of the Spatial Pattern Randomness for the Wafer Map Benchmarks,” in Proc. IEEE VLSI Test Symposium (VTS), Apr. 2020. doi :
[71] L.-F. Tseng, Ken C.-C. Cheng, J.-D. Li, K. S.-M. Li, and S.-J. Wang, "Test System Parametric Yield Prediction Using Machine Learning Techniques," in Proc. IEEE VLSI Test Symposium (VTS), Apr. 2020. doi :
[72] D.-C. Hu, H. Hashimoto, L.-F. Tseng, K. C.-C. Cheng, K. S.-M. Li, S.-J. Wang, S. Y.-S. Chen, J.E. Chen, C. Y.-H. Liu, and A. Y.-A. Huang, "Innovative Practice on Wafer Test Innovations," in Proc. IEEE VLSI Test Symposium (VTS), Apr. 2020. doi : 10.1109/VTS48691.2020.9107619
[73] K. S.-M. Li, P. Y.-Y. Liao, L. Chou, K. C.-C. Chen, A. Y.-A. Huang, S.-J. Wang, and G. C.-H Han, “PWS: Potential Wafermap Scratch Defect Pattern Recognition with Machine Learning Techniques,” in Proc. IEEE European Test Symposium (ETS), May 2020. doi : 10.1109/ETS48528.2020.9131598
[74] T.-P. Hong, C.-Y. Lin, W.-M. Huang, K. S.-M. Li, S.-L. Wang, and J. C.-W. Lin, "One-Phase Temporal Fuzzy Utility Mining," in Proc. IEEE International Conference on Fuzzy Systems (FUZZ-IEEE), July 2020. doi : 10.1109/FUZZ48607.2020.9177621
[75] T.-P. Hong, C.-Y. Lin, W.-M. Huang, K. S.-M. Li, S.-L. Wang, and J. C.-W. Lin, "Mining High Fuzzy Average-Utility Itemsets," in Proc. International Conference on System Science and Engineering (ICSSE), Aug. 2020.
[76] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Watermarking for Paper-Based Digital Microfluidic Biochips,” in Proc. IEEE International Test Conference in Asia (ITC-Asia), Sep. 2020. doi : 10.1109/ITC-Asia51099.2020.00037
[77] S. J.-H. Su, T.-P. Hong, Y.-H. Hsieh, and K. S.-M. Li, “Effective Music Emotion Recognition by Segment-based Progressive Learning,” in Proc. IEEE International Conference on Systems, Man, and Cybernetics (SMC), Oct. 2020. doi : 10.1109/SMC42975.2020.9283500
[78] L. L.-Y. Chen, K. S.-M. Li, K. C.-C. Cheng, S.-J. Wang, A. Y.-A. Huang, N. C.-Y. Tsai, L. Chou, and C.-S. Lee, “TestDNA-E: Wafer Defect Signature for Pattern Recognition by Ensemble Learning,” in Proc. IEEE International Test Conference (ITC), Nov. 2020. doi : 10.1109/ITC44778.2020.9325237
[79] T.-P Hong, M.-P. Ku, W.-M. Huang, K. S.-M. Li, and J. C.-W. Lin, “A Tree-based Fuzzy Average-Utility Mining Algorithm,” in Proc. International Conference on Data Mining Workshops (ICDMW), Nov. 2020. doi : 10.1109/ICDMW51313.2020.00094
[80] S.-J. Wang, C.-X. Tsai, Y.-W. Tseng, and K. S.-M. Li, “Feature Selection for Malicious Traffic Detection with Machine Learning,” in Proc. International Computer Symposium (ICS), Dec. 2020. doi : 10.1109/ICS51289.2020.00088
[81] F.-C. Wu, J.-D. Li, K. S.-M. Li, S.-J. Wang, and T.-Y. Ho, “Double DQN for Chip-Level Synthesis of Paper-Based Digital Microfluidic Biochips,” in Proc. IEEE Design, Automation & Test in Europe (DATE), Feb. 2021. doi : 10.23919/DATE51398.2021.9474065
[82] S.-J. Wang, T.-H. Chang, and K. S.-M. Li, “Machine Learning Assisted Challenge Selection for Modeling Attack Resistance in Strong PUFs,” in Proc. IEEE International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2021. doi : 10.1109/VLSI-DAT52063.2021.9427337
[83] K. S.-M. Li, L. L.-Y. Chen, P. Y.-Y. L., K. C.-C. Cheng, S.-J. Wang, A. Y.-A. Huang, L. Chou, N. C.-Y. Tsai, C.-S. Lee, G. C.-H. Han, J. E Chen, H.-C. Liang, and C.-L. Hsu, “Automatic Inspection for Wafer Defect Pattern Recognition with Unsupervised Clustering,” in Proc. IEEE European Test Symposium (ETS), May 2021. doi : 10.1109/ETS50041.2021.9465457
[84] K. S.-M. Li, L. L.-Y. Chen, P. Y.-Y. Liao, S.-J. Wang, A. Y.-A. Huang, and K. C.-C. Cheng, “Integrated Scratch Marker for Wafer Defect Diagnosis,” in Proc. IEEE International Test Conference in Asia (ITC-Asia), Aug. 2021. doi : https://www.aconf.org/conf_180631/contribution/69.html
[85] P. Y.-Y. Liao, K. S.-M. Li, L. L.-Y. Chen, S.-J. Wang, A. Y.-A. Huang, K. C.-C. Cheng, C.-Y. Tsai, and L. Chou, “WGrid: Wafermap Grid Pattern Recognition with Machine Learning Techniques,” in Proc. IEEE International Test Conference (ITC), Oct. 2021. doi : 10.1109/ITC50571.2021.00043
[86] L. L.-Y. Chen, K. S.-M. Li, X.-H. Jiang, S.-J. Wang, A. Y.-A. Huang, J. E. Chen, H.-C. Liang, and C.-L. Hsu, “Semi-Supervised Framework for Wafer Defect Pattern Recognition with Enhanced Labeling,” in Proc. IEEE International Test Conference (ITC), Oct. 2021. doi : 10.1109/ITC50571.2021.00029
[87]T.-P. Hong, H. Chang, K. S.-M. Li and Y.-C. Tsai, “A Unified Temporal Erasable Itemset Mining Approach,” in Proc. International Conference on Technologies and Applications of Artificial Intelligence (TAAI), Nov. 2021. doi : 10.1109/TAAI54685.2021.00044.
[88]T.-P. Hong, H. Chang, K. S.-M. Li and Y.-C. Tsai, “A Dedicated Temporal Erasable-Itemset Mining Algorithm,” in Proc. International Conference on Intelligent Systems Design and Applications (ISDA), Dec. 2021. doi : 10.1007/978-3-030-96308-8_91
[89] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Design-for-Reliability and Probability-Based Fault Tolerance for Paper-Based Digital Microfluidic Biochips with Multiple Faults,” in Proc. ACM/IEEE Asia and South Pacific Design Automation Conference (ASPDAC), Jan. 2022. doi : 10.1109/ASP-DAC52403.2022.9712521
[90] S.-J. Wang, Y.-C. Shih, K. S.-M. Li, C.-Y. Lin, and S.-K. Chong, “Improving IJTAG Test Efficiency and Security,” in Proc. International Symposium on VLSI Design, Automation and Test (VLSI-DAT), Apr. 2022. doi : 10.1109/VLSI-DAT54769.2022.9768048
[91] N. Sinhabahu, J.-D. Li, K. S.-M. Li, S.-J. Wang, and T.-Y. Ho, “Trojan Insertions of Fully Programmable Valve Arrays,” in Proc. IEEE European Test Symposium (ETS), May 2022. doi : 10.1109/ETS54262.2022.9810384
[92] L. L.-Y. Chen, K. S.-M. Li, S.-J. Wang, A. Y.-A. Huang, C.-S. Lee, K. C.-C. Cheng, P. Y.-Y. Liao, and L. Chou, “Compositive Framework for Wafer Pattern Recognition with Confidence Relabeling Technique,” in Proc. IEEE International Test Conference (ITC), Sep. 2022 (Poster). doi :
[93] K. C.-C. Cheng, K. S.-M. Li, S.-J. Wang, A. Y.-A. Huang, C.-S. Lee, L. L.-Y. Chen, P. Y.-Y. Liao, and N. C.-Y. Tsai, “Wafer Defect Pattern Classification with Explainable-Decision Tree Technique,” in Proc. IEEE International Test Conference (ITC), Sep. 2022. doi : 10.1109/ITC50671.2022.00070
[94] N. Sinhabahu, K. S.-M. Li, J.-D. Li, J. R. Wang, and S.-J. Wang, “Yield-Enhanced Probe Head Cleaning with AI-Driven Image and Signal Integrity Pattern Recognition for Wafer Test,” in Proc. IEEE International Test Conference (ITC), Sep. 2022. doi : 10.1109/ITC50671.2022.00071
[95] S.-J. Wang, Y.-C. Lin, C.-Y. Lin, S.-K. Chong, K. S.-M. Li, “Automatic Alignment for Side-Channel Attack Against Cryptographic Modules,” in Proc. IET International Conference on Engineering Technologies and Application (IET ICETA), Oct. 2022. doi : 10.1109/IET-ICETA56553.2022.9971560
[96] S.-J. Wang, K. S.-M. Li, C.-Y. Lin, and S.-K. Chong, “Intrusion Detection and Obfuscation Mechanism for PUF-Based Authentication,” in Proc. IEEE Asian Test Symposium (ATS), Nov. 2022. doi : 10.1109/ATS56056.2022.00028
[97] N. Sinhabahu, K. S.-M. Li, S.-J. Wang, J. R. Wang, and M. Ho, “Machine-Learning Driven Sensor Data Analytics for Yield Enhancement of Wafer Probing,” in Proc. IEEE International Test Conference (ITC), Oct. 2023. doi : 10.1109/ITC51656.2023.00023
[98] T.-P. Hong, M.-P. Ku, Y.-C. Tsai, W.-M. Huang, and K. S.-M. Li, “Trade-off Between Execution Time and Memory Consumption in Fuzzy Average-Utility Mining,” in Proc. International Conference on Awareness Science and Technology (iCAST), Nov. 2023. doi : 10.1109/iCAST57874.2023.10359302
[99] T.-P. Hong, M. J. Kuo, C.-H. Chen, K. S.-M. Li, “Federated Erasable-itemset Mining with Quasi-erasable Itemsets,” in Proc. Asian Conference on Intelligent Information and Database Systems (ACIID), Apr. 2024. doi :
[100] T.-P. Hong, R. Lee, B. Vo, K. S.-M. Li, “Metamorphic Testing of High-Utility Itemset Mining,” in Proc. International Workshop on Utility-Driven Mining and Learning (UDML), May 2024. doi : [BACK TO TOP]

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III. Domestic Conferences:
[1] K. S.-M. Li, Y.-H. Cherng and Y.-W. Chang, “Noise-Aware Buffer Planning for Interconnect-Driven Floorplanning,” in Proc. VLSI Design/CAD Symposium, Aug. 2002.
[2] K. S.-M. Li, C.-L. Lee, C. Su and J.-E Chen, “A Unified Approach to Detecting Crosstalk Faults of Interconnects in Deep Sub-micron VLSI,” in Proc. VLSI Design/CAD Symposium, Aug. 2004.
[3] K. S.-M. Li, C.-L. Lee, C. Su, and J.-E Chen, “Oscillation Ring Based Interconnect Test Scheme for SOC,” in Proc. VLSI Design/CAD Symposium, Aug. 2004.
[4] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su, and J.-E Chen, “IEEE Standard 1500 Compatible Interconnect Diagnosis for Delay and Crosstalk Faults,” in Proc. VLSI Design/CAD Symposium, Aug. 2005.
[5] K. S.-M. Li, C.-L. Lee, Y.-W. Chang, C. Su and J.-E Chen, “Multilevel Full-Chip Routing with Testability and Yield Enhancement,” in Proc. VLSI Design/CAD Symposium, Aug. 2005
[6] K.-L. Peng, S.-J. Wang and K. S.-M. Li, “Layout-Aware Scan Chain Reorder for Skewed-Load Transition Test Coverage,” in Proc. VLSI Design/CAD Symposium, Aug. 2006.
[7] X.-L. Li, S.-J. Wang and K. S.-M. Li, “Layout-Aware Multi-Layer Multi-Level Scan Tree Synthesis,” in Proc. VLSI Design/CAD Symposium, Aug. 2006.
[8] S.-J. Wang, P.-C. Tsai, H.-M. Weng and K. S.-M. Li, “Test Data and Test Time Reduction for LOS Transition Test in Multi-Mode Segmented Scan Architecture,” in Proc. VLSI Design/CAD Symposium, Aug. 2007.
[9] S.-J. Wang, S.-C. Chen and K. S.-M. Li, “Enhancing Compression Efficiency with Skewed-Probability Scan Chains,” in Proc. VLSI Design/CAD Symposium, Aug. 2007.
[10] J.-Y. Huang and K. S.-M. Li, “Interconnect-Driven Multiple Scan Tree Synthesis for Both Test Compression and Test Application Time,” in Proc. VLSI Test Technology Workshop (VTTW), July 2007.
[11] Y.-W. Liu, J.-Y. Huang and K. S.-M. Li, “IEEE 1500 Compatible Interconnect Oscillation Parallel Test,” in Proc. VLSI Test Technology Workshop (VTTW), July 2008.
[12] K.-L. Fu, S.-J. Wang and K. S.-M. Li, “Low Peak Power ATPG and Test Compaction for n-Detection Test,” in Proc. VLSI Design/CAD Symposium, Aug. 2008.
[13] S.-J. Wang, S.-J. Huang and K. S.-M. Li, “Static and Dynamic Test Power Reduction in Scan-Based Testing by Input Vector Control,” in Proc. VLSI Design/CAD Symposium, Aug. 2008.
[14] K. S.-M. Li, Y.-C. Hung and J.-Y. Huang, “Multiple Scan Trees Synthesis for Test Time/Data and Routing Length Reduction under Output Constraint,” in Proc. VLSI Test Technology Workshop (VTTW), July 2009.
[15] K. S.-M. Li, Y.-Y. Liao, Y.-W. Liu and J.-Y. Huang, “IEEE 1500 Compatible Multilevel Maximal Concurrent Interconnect Test,” in Proc. VLSI Test Technology Workshop (VTTW), July 2009.
[16] S.-Y. Chen and K. S.-M. Li, “Fast Custom Co-Floorplanning NoC Generation,” in Proc. VLSI Design/CAD Symposium, Aug. 2010.
[17] C.-Y. Pai and K. S.-M. Li, “Maximal Resilience for Reliability and Yield Enhancement in interconnect Structure,” in Proc. VLSI Test Technology Workshop (VTTW), Aug. 2010.
[18] C.-Y. Pai, L.-B. Chen, B.-C. Cheng, J.-C. Chen, K. S.-M. Li and J.-J. Chen, “Oscillation Ring Test Scheme for Horizontal/Vertical Interconnects in 3D Integrated Circuits,” in Proc. VLSI Test Technology Workshop (VTTW), July 2011.
[19] B.-C. Cheng, T.-T. Ku, S.-H. Yang, C.-S. Chen, K.-C. Kuo, C.-C. Wang, K-.Y. Hsieh, L.-B. Chen, and K. S.-M. Li, “Fault-Tolerant Communication Modeling for Smart Grid Electric Power Systems,” in Proc. VLSI Test Technology Workshop (VTTW), July 2011.
[20] Y.-X. Zheng, L.-B. Chen, K.-Y. Hsieh and K. S.-M. Li, “Application-Specific NoC Topology Synthesis with Fault Tolerance for 3D ICs,” in Proc. VLSI Design/CAD Symposium, Aug. 2011.
[21] S.-J. Wang, Y. -S Chen and K. S.-M. Li, “Low-Cost Testing of TSVs in 3D Stacks with Pre-bond Testable Dies,” in Proc. VLSI Test Technology Workshop (VTTW), July 2012.
[22] S.-J. Wang, H.-H Hsu and K. S.-M. Li, “Delay Test Scheme for Low-Power Pre-Bond,” in Proc. VLSI Design/CAD Symposium, Aug. 2012.
[23] C.-Y. Ho, S.-J. Wang, R.-T. Gu, J.-J. Huang, B.-C. Cheng, Y.-C. Ho and K. S.-M. Li, “A Layout-Aware Test Methodology for Silicon Interposer in System-in-a-Package,” in Proc. VLSI Test Technology Workshop (VTTW), July 2013.
[24] W.-C. Lien, K.-J. Lee, T.-Y. Hsieh, K. C. and K. S.-M. Li, “An Internal-Response-Based LFSR Reseeding Technique,” in Proc. VLSI Design/CAD Symposium, Aug. 2013.
[25] C.-L. Wu, C.-Y. Ho, S.-Y. Wang and K. S.-M. Li, “Interposer Test for Open Fault,” in Proc. VLSI Test Technology Workshop (VTTW), July 2014.
[26] C.-L. Wu, C.-Y. Ho, S.-Y. Wang and K. S.-M. Li, “Interposer Test for Short Fault,” in Proc. VLSI Design/CAD Symposium, Aug. 2014.
[27] J.-D. Li, S.-J. Wang, T.-Y. Ho and K. S.-M. Li, “Test and Diagnosis of Paper-Based Microfluidic Biochips,” in Proc. VLSI Test Technology Workshop (VTTW), July 2015.
[28] H.-C. Chen and K. S.-M. Li, “Big Data Analysis and Prediction by Machine Learning in High Frequency Trading Application,” in Proc. Cloud Computing and Big Data Analysis Conference (ICCCBDA), July 2016. (Best Paper Award)
[29] S.-J. Wang, J.-Y. Wei, S.-H. Huang and K. S.-M. Li, “Test Generation for Combinational Hardware Trojans,” in Proc. VLSI Test Technology Workshop (VTTW), July 2016.
[30] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Conductive Wire Routing for Pin-Constrained Paper-Based Microfluidic Biochips,” in Proc. VLSI Design/CAD Symposium, Aug. 2016.
[31] J.-L. Wu, T.-Y Ho, K. S.-M. Li and S.-J. Wang, “Flow-based Microfluidic Synthesis Consideration Skew,” in Proc. VLSI Design/CAD Symposium, Aug. 2016.
[32] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “A Diagnosis Method with Fault Tolerance for Paper-Based Microfluidic Biochips,” in Proc. VLSI Design/CAD Symposium, Aug. 2016.
[33] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Detection for Stealthy Combinational Hardware Trojans,” in Proc. VLSI Test Technology Workshop (VTTW), July 2017.
[34] S.-J. Wang, J.-Y. Wei, S.-H. Huang and K. S.-M. Li, “Digital Rights Management for Paper-Based Microfluidic Biochips,” in Proc. VLSI Test Technology Workshop (VTTW), July 2017.
[35] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Co-Placement Optimization of Cyber-Physical Digital Microfluidic Biochips for Testing,” in Proc. VLSI Test Technology Workshop (VTTW), July 2017.
[36] S.-J. Wang, H.-H. Chen, C.-H. Lien and K. S.-M. Li, “Testing Clock Distribution Networks,” in Proc. VLSI Test Technology Workshop (VTTW), July 2017.
[37] S.-J. Wang, C.-H. Lien, Y.-Y. Li and K. S.-M. Li, “Scan PUF with On-Line Evaluation,” in Proc. VLSI Test Technology Workshop (VTTW), July 2018.
[38] J.-D. Li, S.-J. Wang, K. S.-M. Li and T.-Y. Ho, “Design-for-Reliability for Paper-Based Digital Microfluidic Biochips,” in Proc. VLSI Test Technology Workshop (VTTW), July 2018.
[39] J.-L. Wu, K. S.-M. Li, J.-D. Li, S.-J. Wang and T.-Y. Ho, “SOLAR: Skew-Consideration and Optimization of Control-Layer Pins Placement and Channel Routing in Reliable Flow-Based Microfluidic Biochips,” in Proc. VLSI Test Technology Workshop (VTTW), July 2018.
[40] J.-D. Li, A. Y.-A. Huang, K. S.-M. Li, S.-J. Wang, C.-Y. Tsai, K. C.-C. Cheng, X.-H. Jiang, L. Chou and C.-S. Lee, “Wafer Defect Signature for Test and Diagnosis,” in Proc. VLSI Test Technology Workshop (VTTW), July 2019.
[41] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Watermarking for Paper-Based Digital Microfluidic Biochips Security,” in Proc. VLSI Test Technology Workshop (VTTW), July 2019.
[42] P. Y.-Y. Liao, J.-D. Li, K. S.-M. Li, L. Chou, K. C.-C. Cheng, A. Y.-A. Huang, and S.-J. Wang, “Wafermap Scratch Pattern Recognition with Machine Learning Techniques,” in Proc. VLSI Test Technology Workshop (VTTW), July 2020.
[43] K. C.-C. Cheng, J.-D. Li, J.-W. Li, L. L.-Y. Chen, C.-Y. Tsai, P. Y.-Y. Liao, K. S.-M. Li, S.-J. Wang, L. Chou, C.-S. Lee, and A. Y.-A. Huang, “Site Dependence Detection with Artificial Intelligence in Wafer Test,” in Proc. VLSI Test Technology Workshop (VTTW), July 2020.
[44] L. L.-Y. Chen, J.-D. Li, K. C.-C. Cheng, C.-Y. Tsai, P. Y.-Y. Liao, K. S.-M. Li, S.-J. Wang, L. Chou, C.-S. Lee, and A. Y.-A. Huang, “Wafer Defect Signature for Pattern Recognition by Ensemble Learning,” in Proc. VLSI Test Technology Workshop (VTTW), July 2020.
[45] J.-D. Li, S.-J. Wang, K. S.-M. Li, and T.-Y. Ho, “Enhanced Watermarking Scheme for Paper-Based Digital Microfluidic Biochip,” in Proc. VLSI Test Technology Workshop (VTTW), July 2020.
[46] J.-H. Su, T.-P. Hong, Y.-H. Hsieh, K. S.-M. Li, “Enhanced Music Emotion Recognition by Applying Deep Learning to Music Fragments,” in Proc. National Conference on Web Intelligence and Applications (NCWIA), July 2020.
[47] K. S.-M. Li, C. Wen, T.-C. Huang and S.-Y. Huang, “Test-for-Zero: The Future Roadmap of Test Methodology Towards Zero Failure Rate,” in Proc. VLSI Design/CAD Symposium, Aug. 2020.
[48] T.-P. Hong, C.-Y. Lin, W.-M. Huang, K. S.-M. Li, and M.-P. Ku, “使用較複雜樹狀結構探討高時序性模糊效益項目集,” in Proc. International Conference on Fuzzy Theory and Its Applications (iFUZZY), Nov. 2020.
[49] N. Sinhabahu,K. S.-M. Li, S.-J. Wang, J. R. Wang, M. Ho, “Enhancing Semiconductor Testing Accuracy with a Machine Learning-Driven Approach for Probe Card Repair Verification,” accepted by VLSI Design/CAD Symposium, June 2024.

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Edited by Jian-De Li, 2020/11/15